This invention relates to logic circuitry and in particular to counters used as part of VSLI circuits.
Many of the counters available use a flip-flop circuit and a series of logic gates for each bit of the counter. The logic gates used typically increase in complexity as the number of bits of the counter increases, and in addition the numbers of interconnections between bits increase with an increase in the number of bits. This results in layout problems for the integrated circuit designer and causes a greater area of silicon to be needed than is, in many cases, desirable.
It is desirable to have a multibit capacity counter circuit which comprises a standard stage which can be coupled to other identical stages to form the desired bit capacity counter without the interconnections between adjacent stages increasing as the number of needed bits increases. Such a counter offers simplicity of design and silicon area efficiencies.